1. Field of the Invention
The present invention is directed to a method for polysilicon crystalline (PC) line width measurement post etch in undoped-polysilicon process, and more particularly, to a method for in line electrical measurement of a polysilicon (poly) line width dimension post PC etch prior to doping of the poly.
2. Discussion of the Prior Art
Advanced CMOS and MOSFET circuits, such as 0.35 .mu.m and 0.25 .mu.m generation circuits, have increasingly narrow gate sizes, that are formed by etching a polysilicon layer. After etching the polysilicon layer, which is undoped and also referred to as an intrinsic poly layer, the dimension of the remaining gate is measured to ascertain that the remaining polysilicon gate has the desired dimension, such as the desired line width. Measuring the poly gate line width is typically used for controlling the effective channel length, L.sub.eff, located in the substrate below the poly gate and along the gate width between the source and drain of the MOSFET.
MOSFETs having a short effective channel length L.sub.eff are desirable, since they are smaller and operate at higher and faster frequencies. Short channel lengths also require narrow gate widths. Typically, the length of the channel is approximately the width of the poly gate.
Conventional measurements of channel lengths or poly gate widths have been performed by measuring electrical characteristics of the poly gate after doping thereof. Doping the poly gate is necessary in order to render the poly gate electrically active so that electrical measurements can be performed. From the electrical measurements of the doped poly gate, the quality of the poly layer etch that patterns and forms the poly gate is determined. In particular, the dimension, such as the width, of the patterned poly gate is determined from the electrical measurements of the doped poly gate.
During semiconductor device or MOSFET integrated circuit (IC) fabrication, due to the increasingly small gate dimensions, rapid feedback of the MOSFET poly layer etch that forms the gate, and measurement of the gate line width, are no longer achieved due to the use of undoped polysilicon in 0.5 .mu.m through 0.25 .mu.m generation integrated circuits (ICs), for example. Further, since undoped polysilicon is not a good electrical conductor, it is not possible to electrically determine the width of the polysilicon gate, hence the quality of the polysilicon layer etch that forms the gate, by measuring electrical characteristics of the undoped polysilicon gate.
The inability to rapidly measure polysilicon gate line widths delays electrical characterization of the MOSFET ICs several weeks, where in the meantime, other process steps have been completed. For example, electrical characterization is delayed to post source/drain anneal. This results in a greater risk to the wafer in process for sorting the manufactured MOSFETs according to their operating speed, which is directly related to the channel length or the gate width.
Accordingly, there is a need to provide a method to accurately and rapidly measure electrical characteristics of intrinsic/undoped or lightly doped polysilicon lines to determine line widths thereof.